1. Field of the Invention
The present invention relates to a dual-gate CMOS semiconductor device and a dual-gate CMOS semiconductor device manufacturing method. More specifically, the present invention relates to a dual-gate CMOS semiconductor device and a dual-gate CMOS semiconductor device manufacturing method capable of reducing the mutual diffusion of impurities in a gate electrode.
2. Description of Related Art
In recent years, CMOS semiconductor devices of a dual-gate structure have been adopted with a view of improving performance and reducing power consumption. As the gate electrodes of this dual-gate structure, a polycrystalline silicon layer containing N type impurities such as arsenic is used on an NMOS part and a polycrystalline silicon layer containing P type impurities such as boron is used on a PMOS part.
The semiconductor device of such a dual-gate structure is disclosed by, for example, “M. Togo, et al., Thermal Robust Dual-Gate CMOS Integration Technologies for High-Performance DRAM-Embedded ASCIs', IEDM Technical Digest, p. 49 (1999)”.
According to the above-cited document, a so-called W polyside structure in which a WSi2 layer is built up on a polycrystalline silicon layer, is used as a gate electrode. This gate electrode is normally employed in a device having a mixture of a DRAM and Logic. In addition, for the purpose of realizing higher integration, a so-called SAC structure for providing contacts on a source/drain layer in a self-aligned manner to a gate electrode by forming a nitride film on the WSi2 layer and also forming a nitride film on a sidewall.
The conventional dual-gate CMOS semiconductor device, however, has the following disadvantages. A heat treatment is conducted to form elements after the formation of a gate electrode. Due to this, impurities contained in a polycrystalline silicon layer on an NMOS part and those contained in a polycrystalline silicon layer on a PMOS part are mutually diffused through the WSi2 layer. In other words, N type impurities are introduced into the polycrystalline silicon layer on the PMOS part and P type impurities are introduced into the polycrystalline silicon layer on the NMOS part, with the result that the performance of the semiconductor device disadvantageously deteriorates.